Myers Research Group

University of Utah



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High-Level Synthesis of Asynchronous Systems

SUPPORTED BY

NSF CAREER award MIP-9625014


We have developed methods for specifying timed systems at either the channel or handshaking level using standard VHDL. These methods allow bounded timing constraints to be specified on all signal transitions. This information will be used throughout the synthesis process to optimize the circuit which is produced. These descriptions are automatically compiled into a timed event/level (TEL) structure description. TEL structures were developed by Wendy Belluomini. The compiler from VHDL to TEL structures was developed by Hao Zheng. Eric Peskin extended this compiler to support channel-level VHDL and to compile to handshaking-level TEL structures. His compiler explores many alternative protocols and selects the best for synthesis. Publications describing this work are listed below.

We have also developed a new design tool for automatically generating asynchronous data paths. This tool is capable of efficiently exploring thousands of potential architectures and reporting the smallest and fastest designs. This work was conducted by Brandon Bachman.

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