NSF-9991168: Design Methodology for Mixed Analog/Asynchronous VLSI Implementations of Communications Systems

As transistor feature sizes move towards 0.1um and clock frequencies exceed a GHz, it is becoming increasingly difficult to develop schemes to distribute a global clock. These difficulties are causing many researchers to consider alternatives to the traditional globally synchronous digital systems. Two possible alternatives are analog and asynchronous design which both have the added potential of higher performance and lower power. The goal of this research is to develop and apply a design methodology for mixed analog/asynchronous circuits. We plan to use driving examples from the field of communications due to their challenging performance and power demands. The asynchronous nature of communications systems coupled with recent analog implementations of probability propagation algorithms (PPA), a key operation in such systems as turbo codes, makes this field a prime target for potential gains.

We plan to extend our work in the area of iterative decoding using probability propagation to develop algorithms and architectures which can take advantage of the properties of a mixed analog/asynchronous system. We plan to apply the CAD tools that we have been developing for timed asynchronous circuit design to learn their strengths and weaknesses in the face of a large, practical design. Finally, we plan to develop new circuit design methodology for the implementation of mixed analog/asynchronous systems.

We intend for our design methodology development to be completely driven by practical design examples. To this end, we plan to:

The chip plot shown above is our first prototype which is an implementation of the (8,4) extended Hamming code.